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Espressif Systems /ESP32-P4 /H264_DMA /RST_CONF

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Interpret as RST_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INTER_AXIM_RD_RST)INTER_AXIM_RD_RST 0 (INTER_AXIM_WR_RST)INTER_AXIM_WR_RST 0 (EXTER_AXIM_RD_RST)EXTER_AXIM_RD_RST 0 (EXTER_AXIM_WR_RST)EXTER_AXIM_WR_RST 0 (CLK_EN)CLK_EN

Description

axi reset config register

Fields

INTER_AXIM_RD_RST

Write 1 then write 0 to this bit to reset axi master read data FIFO.
INTER_AXIM_WR_RST

Write 1 then write 0 to this bit to reset axi master write data FIFO.
EXTER_AXIM_RD_RST

Write 1 then write 0 to this bit to reset axi master read data FIFO.
EXTER_AXIM_WR_RST

Write 1 then write 0 to this bit to reset axi master write data FIFO.
CLK_EN

1’h1: Force clock on for register. 1’h0: Support clock only when application writes registers.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd